| 摘要 |
PURPOSE:To improve an execution efficiency by reducing an address arithmetic operation to invalid data when the invalid data is successive. CONSTITUTION:A value obtained by multiplying a distance between elements by one - three is added once by inputting the distance between the elements shifted by one bit leftward to the residual input of a three input adder 1. When more than three invalid data is successive, selection signals 109 - 111 to select an address register output 113, an output 115 of one bit leftward shift circuit 5 and a distance 105 between the elements respectively are sent to selection circuits 2 - 4 and a memory access request 114 is not sent to a memory access controller. The three input adder 1 inputs the outputs 106 - 108 of the selection circuits 2 - 4 to feed an addition output 112 to an address register 6 and the memory access controller. |
