发明名称 CHIP TYPE DELAY ELEMENT
摘要 PURPOSE:To be low in an actually loading height, small and to facilitate a delaying time adjustment by making a conducting chip substrate into an earth electrode, forming a desired snacked delaying line pattern on a insulating layer formed at a conductive chip substrate and providing further a pat at both terminals of a delay line pattern and a bending part. CONSTITUTION:On the whole surface of the surface of a conductive chip substrate 11, an insulating layer 12 composed of the oxide film formed, and a snaked delay line pattern 13 having a desired long line length is formed on the insulating layer 12. A terminal pat 14 is formed at both terminals of the delay line pattern 133 so that a chip type delay element can be serially connected through a terminal line 16 to a signal line 22 of a circuit substrate 20. Further, an intermediate pat 15 is formed at respective bending parts of the delay line pattern 13, and through a short-circuit line 17, the mutual section of a selected intermediate pat 15 or the selected intermediate pat 15 and the terminal pat 14 are short-circuited. Consequently, the conductive chip substrate 11 can be miniaturized. After actually loading onto the circuit substrate 20, through the short-circuit line 17, the mutual section between the selected intermediate pat 15 or the selected intermediate pat 15 and the terminal pat 14 are short- circuited, and the delaying time can be easily adjusted.
申请公布号 JPS63139402(A) 申请公布日期 1988.06.11
申请号 JP19860288040 申请日期 1986.12.02
申请人 FUJITSU LTD 发明人 HIROSE ATSUKO;SUGIKI HIROYASU;TSUBONE KENICHIRO;SUZUKI YUKO
分类号 H01P9/00;H03H7/30 主分类号 H01P9/00
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