发明名称 DYNAMIC MEMORY
摘要 PURPOSE:To decrease a current consumed with a substrate voltage generating circuit by providing a control means to suspend a substrate voltage generating circuit at the time of holding data and other substrate voltage generating circuit to generate a substrate voltage based on an external clock. CONSTITUTION:A RAS type timing generating circuit 1 generates a RAS type timing with an external clock inversion RAS as an input. The clock inversion RAS is connected through a buffer 6 to the input of a charging pump 5 of a reference voltage generating circuit through a buffer 6. On the other hand, another side reference voltage generating circuit is composed of an oscillator 2 and a charging pump 3. The oscillator 2 connects a refresh input signal inversion RFSH through a PMOS transistor P1, in which a signal inverted by an inverter 7 is connected to a gate, to a power source voltage VC. At the time of a signal inversion RFS low level, the oscillation of the oscillator 2 is stopped. Thus, the current consumed by the oscillator 2 and the pump 3 can be eliminated.
申请公布号 JPS63138594(A) 申请公布日期 1988.06.10
申请号 JP19860285100 申请日期 1986.11.28
申请人 NEC CORP 发明人 INAGAKI YASABURO
分类号 G11C11/408;G11C11/34 主分类号 G11C11/408
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