发明名称 ANNEALING DEVICE FOR COMPOUND SEMICONDUCTOR SUBSTRATE
摘要 PURPOSE:To shift the distribution of carriers in a compound semiconductor substrate to the interface side, and to shallow an implantation layer by mounting an annealing furnace annealing the substrate and an electric field applier, which is installed inside or outside the annealing furnace and vertically applies an electric field to the substrate. CONSTITUTION:A P-type or N-type impurity implanted in a compound semiconductor substrate 13 is activated through annealing, and a P-type or N-type conductive layer is each formed. The device is provided with an annealing furnace 1 annealing the substrate 13 and an electric field applier 3, which is set up inside or outside the annealing furnace 1 and vertically applies an electric field to the substrate 13. Accordingly, carrier concentration near the interface at the annealing time when protective films 15 are shaped on the compound semiconductor substrate 13 or at the annealing time when no protective film 15 is formed is increased, thus improving the electrical characteristics of an ion implantation layer 14-particularly, carrier distribution is concentrated near the interface, then acquiring shallow carrier distribution.
申请公布号 JPS63138741(A) 申请公布日期 1988.06.10
申请号 JP19860284245 申请日期 1986.12.01
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 YAMAGUCHI NAKAHIKO
分类号 H01L21/326;H01L21/265;H01L21/324;H01L21/338;H01L29/80;H01L29/812 主分类号 H01L21/326
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