| 摘要 |
PURPOSE:To execute accurate discrimination, reproduction and relaying even if the number of relaying stages are increased by providing delay means which delay an extracted clock in at least two relaying stages among plural relaying stages and causing the delay time of the timing clock by means of the delay means to respectively differ. CONSTITUTION:A clock delay part 15 for delaying the extracted clock is provided on the side of the output of a clock extraction part 1A which has a prescribed delay time decided by a circuit constant or the like. The extracted clock from the clock extraction part 1A is given to a discrimination reproduction part 2A in a waveform delayed by this delay time. Relaying stages A and B respectively have clock delay parts and the delay time by these clock delay parts differ in the relaying stages A and B. If the delay time of the clock delay part in the relaying stage A is set to tdA, and that in the relaying stage B is to tdB, it shows tdAnot equal to tdB. Thus, the position of jitter appearing in the extracted clock can be differed in respective relaying stages. |
