发明名称 SYNCHRONIZING CONTROLLER
摘要 PURPOSE:To control an offset by a word unit and to enable the control with extremely high precision by monitoring the difference of the number of words which is caused by phase difference after the coincidence of the phases and varying the frequency of a clock signal. CONSTITUTION:In a PLL circuit 8 the division ratio can be altered with a control signal and the clock signal VRCK gradually alters to the one having the deviation of phases from a state where the phase of the clock signal VRCK coincides with the phase of a clock signal WDCK. The difference of the numbers of clocks, in this case, is detected. A control part 9 supplies a deviation control signal to the PLL circuit 8 and alters the frequency of the clock VRCK at speed which can be changed as an information signal recording/reproducing device follows the alteration of the clock VRCK. At this time, the difference of the number of words between the clock WDCK and VRCK is monitored and controlled so as to coincide with quantity which is the target value of multiplication value of the difference of the number of words. Therefore two information signal recording/reproducing devices can be actuated with a specified offset by means of the high resolution of word unit.
申请公布号 JPS63136824(A) 申请公布日期 1988.06.09
申请号 JP19860283944 申请日期 1986.11.28
申请人 SONY CORP 发明人 SETOGAWA TOSHIAKI;ISHII TADAAKI
分类号 H03L7/181;G11B15/46;H03L7/00;H03L7/06;H03L7/08;H04L7/02;H04L7/033 主分类号 H03L7/181
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