| 摘要 |
PURPOSE:To quickly process the transposition of many arrays of bits with a small number of hardwares by controlling shift registers having as same number of stages as the number of lines of data bus lines connected to the respective data bus lines and reading the data in all the registers of an optional shift register in a batch. CONSTITUTION:The shift registers 1a-1h, in eight stages, are respectively constituted in order to shift to an MSB side by one bit every time one bit of data is written on an LSB side and a bus line 5 for writing, consisting of eight data lines, is connected in order to write eight bits(one bite) of data transmitted from the port 2 of a CPU in the LSB sides of the shift registers 1a-1h. And a bus line 6 for incorporation in common, consisting of eight data lines, is connected to fetch the outputs of eight bits of data from the MSB to the LSB of all the shift registers 1a-1h. Thus with a small number of harwares the transposition of bit arrays can be quickly executed.
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