| 摘要 |
A clock generator circuit (10) receives an input signal PPCO and generates a delayed clock output signal PCO. The circuit (10) is set to an initial condition by a precharge signal PCOR prior to a transition of the input signal PPCO. A time delay signal is produced at a node (26) by operation of transistors (18, 28). The transition of the input signal PPCO produces a bootstrapped voltage at a capacitor (68). The delay signal activates a transistor (80) to couple the bootstrapped voltage to the gate terminal of an output transistor (88). The gate terminal of the output transistor (88) is driven directly from a low voltage state to a boosted high voltage state. This causes the output signal PCO to be driven from an initial low voltage state to the power supply voltage Vcc without intervening steps. The output transistors (88, 90) of circuit (10) are never activated at the same time, thereby preventing any current spike from being propagated through the circuit (10). |
