RF modem with improved clock recovery circuit.

摘要

In recovering clock information from received data, the voltage input to a voltage controlled oscillator (Q1) forming part of a phase locked loop (Q1, U3A, U2A, U3B, R10, C12, U4) is determined by comparing a voltage signal to a voltage reference that is precisely the midpoint of the voltage swing between a logic 0 and a logic 1 in the circuit. The voltage reference is generated using an exclusive OR gate (U3B) having one input tied to either the circuit voltage representing a logic 0 or the circuit voltage representing a logic 1. The second input to the exclusive OR gate (U3B) switches between a logic 1 and a logic 0 periodically such that the output of the exclusive OR gate (U3B) switches between the voltage level of a logic 1 and the voltage level of a logic 0 with a 50 percent duty cycle. An exclusive OR gate (U3C) is also used as a phase detector (U3C) to detect the phase difference between a clock signal derived from the phase locked loop oscillator 0output and the received data. The phase detector (U3C) output is compared (U4) to the reference voltage; any difference therebetween adjusts the input voltage to the voltage controlled oscillator and therefore the output frequency of the oscillator (Q1) to maintain a phase difference between the clock signal (CLK) derived from the oscillator (Q1) output and the clock signal in the incoming data to permit sampling the incoming data at a 90 degree phase shift. The voltage reference (U3B) and phase detector (U3C) exclusive OR gates are fabricated on the same wafer and have the same resistive load (R10, R12). In this manner, the voltage reference generated by the exclusive OR gate remains precisely at the midpoint of the voltage swing between logic level 0 and logic level 1, inherently compensating for changes in temperature and other effects.