| 摘要 |
PURPOSE:To prevent a crevasse due to a mask misalignment in a manufacturing step from occurring, an electromigration or disconnection of an interconnection from occurring by forming a first layer interconnection on the top of a first layer insulator having an etching stopper layer on a front surface, etching a second insulating layer to form a connecting hole, and forming a second layer interconnection connected to the first layer wiring through the hole. CONSTITUTION:A second layer interconnection 6 is formed on the top of a first layer insulating layer 4 having an etching stopper layer 4B on the front surface, and a second layer insulating layer 7 is formed on the top of the wiring 6. The layer 7 is etched to form a connecting hole 8. Thus, if the interconnection 6 and the hole 8 are displaced at the mask alignment, the etching of the layer 7 can be controlled by the layer 4B. Accordingly, it can prevent a crevasse from being formed at the layer 4 in the hole 8. Since the layer 4B is formed to prevent the crevasse, the electric reliability of a semiconductor integrated circuit device having a multilayer interconnection structure can be improved.
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