| 摘要 |
PURPOSE:To eliminate processing delay with an information processor by performing simultaneously the arithmetic processes of both preceding and next instructions when the preceding instruction is equal to a loading instruction even though an operand conflict occurs between those preceding and next instructions. CONSTITUTION:A lap control circuit 90 produces an operand conflict detecting signal, an operand lap-around indicating instruction signal and a preceding instruction write preventing signal by means of the instruction decoding information received from an entry of an instruction queue 30. The operand conflict detecting signal is sent to an arithmetic control circuit 95 to prevent the next instruction from starting an arithmetic process via a computing element 81. The operand lap-around instruction signal is sent to selectors 87 and 89 for selection of a 2nd operand to be read out by the preceding instruction as a 1st and 2nd operands to be read out by the next instruction. The preceding instruction write preventing signal is sent to the circuit 95 to prevent a case where the result of the arithmetic process carried out by a computing element 80 is written into a general-purpose register 70.
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