| 摘要 |
PURPOSE:To input serial data during the output period of serial data by reading the data serially based on a clock signal specifying one picture element and inputting the data to a latch circuit serially. CONSTITUTION:A clock signal phiy fed through an external terminal CLK is used as a clock signal to specify one picture element and a data line selection signal inputted to a shift register YSR is shifted by the said signal phiy. As a result, the data line is selected sequentially and the storage information of the selected memory cell is outputted to a common data line one after another. A write signal is taken serially from an external terminal DiN via an input circuit IB1 in a shift register WDFF synchronously with the clock signal phiy. That is, in parallel with the serial read by the shift of the shift register YSR, the serial input of the write signal is applied. The signal is sent to the data line of memory array M-ARY1-ARY2 in parallel by the switch circuit SW2.
|
