发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To reduce the time of phase by varying the phase correction of an output frequency corresponding to a phase difference between an input frequency and a comparison frequency. CONSTITUTION:The output phase of an oscillation circuit 3 is varied by using an external control signal for phase correction and an output frequency fo being N-time of an input frequency fi is oscillated. The output frequency fo is frequency-divided to 1/N by a frequency division circuit 4 to form the same comparison frequency fc as the input frequency fi. The phase difference measuring circuit 1 measures the phase difference of lead or lag of the comparison frequency fc with respect to the input frequency fi and outputs the result to the oscillation phase correction circuit 2. Then the oscillation phase correction circuit 2 varies the phase correction corresponding to the lead or lag phase from the phase difference measuring circuit 1, gives an output to the oscillation circuit 3, which varies the phase of the output frequency fo depending on the phase correction being the output of the oscillated phase correction circuit 2 and oscillates a desired output frequency fo.
申请公布号 JPS63135019(A) 申请公布日期 1988.06.07
申请号 JP19860282978 申请日期 1986.11.26
申请人 NEC CORP 发明人 NEGISHI TAKESHI
分类号 H03L7/093;H03L7/08;H03L7/10;H03L7/199 主分类号 H03L7/093
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