| 摘要 |
PURPOSE:To minimize the redundancy of the number of gates, and to execute an efficient test by inserting a write/read-out scanning circuit in accordance with the fault existence confirmation facility of a circuit, and the input facility of a confirming signal. CONSTITUTION:Design data of an IC 10 consisting of a logic circuit group before inserting a scan latch is read from a fundamental data holding part 11, and the confirmation facility of existence of a fault in an input end and an output end of a circuit is calculated by a fault existence confirmation facility calculating part 12. Also, by a control facility calculating part 13, the setting facility of a signal to the input end for confirming a fault is calculated. Subsequently, their rank order is discriminated by rank order discriminating parts 14, 15, and in order from that which is inferior inconfirmation facility, and that which is inferior in control facility, a write/read scanning circuit is inserted, and FFs 1-8 become scan FFs. In this state, a regular scan test and a non-scan test are executed. |
