| 摘要 |
<p>DETECTOR A detector of predetermined patterns of Manchester encoded data signals in which the voltage levels of the half-bit cells of "n" sequential Manchester bit cells, where "n" is an integer greater than zero, are clocked into a shift register, the pattern of 2 "n" voltage levels of 2 "n" half-bit cells of the "n" sequential Manchester bit cells stored in the register at any given time are examined by a programmable logic array which produces an output signal when the pattern of outputs of the shift register corresponds to the predetermined patterns.</p> |
