| 摘要 |
PURPOSE:To obtain the layout of a pattern of a multi-input logic circuit when high integration-density by a method wherein, at the layout of the pattern of the multi-input logic circuit having m stages (where m is an integer of more than 2), a pre-charging part and a sense-upgrading part are blocked into one part having m' stages (where m' is an integer of less than m but more than 2) and the width of the layout of the prescribed pattern of each block is made identical to the width of the layout of the pattern for the m' stages of a logic- deciding part. CONSTITUTION:Pch MOS transistor P1, P2, P3, P4, for pre-charging use, and sense-upgrading parts S1, S2, S3, S4, covering 4 stages of a pre-charging part and a sense-upgrading part, are combined appropriately, and, for example, S1, P1, P2 and S2 are arranged in an identical row in this sequence while S4, P4, P3 and S3 are arranged in an identical row in this sequence; they are all laid out by a prescribed pattern after they are collected as one block. A width WC of the layout of the prescribed pattern for this one block is made equal to a width 4XWA of the layout of the pattern covering the four stages of a logic-deciding part.
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