| 摘要 |
PURPOSE:To increase operating speed and to decrease the layout pitch of word lines by connecting a main word line bridged over plural sub cell arrays to the subgate word lines connected to a switch gate in a subcell array dividing the main cell array into plural numbers in the column direction via an MIS transistors (TRs). CONSTITUTION:When the voltage of a word line activating signal RA is led from a low level to a high level with the voltage of a decoder output Xi selected by an X decoder at a high level, the voltage of the main word line Woi at first is increased from a high level from a low level. Simultaneously, two signals of either X0, X2 or X1, X3 selected by the signal of X address are kept to a high level and one voltage of subword lines Wi, Wj or Wi+1, Wj+1 is led from a low level to a high level. The information in a memory cell coupled with the subword lines is read to a digit line connected to the cell. The sense amplifier 2 is activated by the resulting potential difference caused and the data is transferred to an external part by a Y decoder and an input/output circuit.
|
