发明名称 METHOD AND APPARATUS FOR REDUCING BIT-RATE
摘要 The method is intended especially for video signals in which so- called coefficient blocks occur as an intermediate signal. The majority of the signal values belonging to a coefficient block - also referred to as coefficients - are 0. For this reason, an uninterrupted sub-string of zeroes is combined with the subsequent coefficient to form an event, provided that the length of the sub-string of zeroes remains below a maximum value. Once the maximum value has been reached, this maximum sub-string of zeroes, along with the subsequent coefficient, is regarded as an event and subsequent coefficients are combined to form further events. A Huffmann code word is allocated to each event for transmission purposes. To form events from the coefficient string, the coefficients are fed via an input line (e) to a comparator circuit (K) and to the address inputs of a memory (PROM). The count of a counter (Z) is supplied to further address inputs of the memory (PROM) and also to the comparator (K). If a coefficient on the input line (e) is 0, the comparator sends a counting pulse to the counter (Z), provided that a maximum count has not yet been reached. If the coefficient at the input (E1) of the comparator (K) has a non-zero value, or the maximum count has been reached, the comparator (K) sends a reset pulse to the counter (Z), with which the code word occurring at the memory (PROM) is simultaneously transferred into a flip-flop circuit (FF). <IMAGE>
申请公布号 JPS63132530(A) 申请公布日期 1988.06.04
申请号 JP19870228698 申请日期 1987.09.14
申请人 PHILIPS GLOEILAMPENFAB:NV 发明人 PEETAA FUOOGERU
分类号 H03M7/40;G06T9/00;H03M7/42;H04N7/26;H04N7/30 主分类号 H03M7/40
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