发明名称 DATA FLOW CONTROL PROCESSOR
摘要 PURPOSE:To attain a processing interruption by cancelling an instruction issu ance and stopping a processing with a link memory, etc., when marking is detected with an instruction packet from an operand memory when the instruc tion issuance is detected. CONSTITUTION:When the sub-instruction packet of an instruction memory 2 is detected by a detecting part 3 and the instruction reading of an address specified beforehand is detected, the stopping instruction to an operand memory 5 is given to the sub-instruction packet. When the stopping instruction is detected to an instruction packet from the memory 5 with a stopping control part 13, a stopping instruction is issued to a link memory 1, the memory 5 and arithmetic sub-modules 6a-6c, the action of the memory 5 is instantaneously stopped, and at the memory 1 and the modules 6a-6c, the action is stopped after the processing, which is being presently executed, is completed.
申请公布号 JPS63131233(A) 申请公布日期 1988.06.03
申请号 JP19860276558 申请日期 1986.11.21
申请人 HITACHI LTD;NIPPON TELEGR & TELEPH CORP <NTT> 发明人 IWAMOTO YOSHIHARU;MASUO KAZUYUKI
分类号 G06F15/82;G06F9/44 主分类号 G06F15/82
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