发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To improve processing speed by detecting whether or not M pieces of operational means, required by M pieces of decoded instructions, are all dead and waiting the operational execution of the instruction while the detected result is negative. CONSTITUTION:Decoding M pieces of instructions and the reading of an operand are simultaneously executed in an instruction controller 2 N, which is not less than M, the number of computing elements E1-EN are controlled in a parallel operation control circuit 5. An operation execution starting signal BOPi is transmitted at every computing element Ei and an operation execution completing signal EOPi is received from each computing element Ei. And the on/off of each signal EOPi is detected in the circuit 5 and the operational execution of a following instruction group is waited until all the computing elements E1-EN are dead.
申请公布号 JPS63131230(A) 申请公布日期 1988.06.03
申请号 JP19860276554 申请日期 1986.11.21
申请人 HITACHI LTD 发明人 SHINTANI YOICHI;KURIYAMA KAZUNORI;SHONAI TORU;KAMATA EIKI;INOUE KIYOSHI
分类号 G06F9/38 主分类号 G06F9/38
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