发明名称 VITERBI DECODER
摘要 PURPOSE:To reduce the circuit scale by selecting the capacity of a trace memory as a capacity to store on the information by several symbols at the end of the maximum likelihood path. CONSTITUTION:The trace memory 5 storing the node number calculated by a node number calculation section 4 by only several symbols of the end of the maximum likelihood path. A branch metric is calculated from the reception code by a distributer 1, and a path metric and a path select signal representing the history of the maximum likelihood path are outputted from an ACS circuit 2 and the path select signal is written in a path memory 3. Based on the path select signal read from the path memory 3, the node number is calculated at a node number calculation section 4 and written in the trace memory 5. As a decoding data, since several symbols of the end of the maximum likelihood path are used, the decoded output is obtained by the several symbols at the end of the maximum likelihood path of the node number written in the trace memory 5.
申请公布号 JPS63129714(A) 申请公布日期 1988.06.02
申请号 JP19860275320 申请日期 1986.11.20
申请人 FUJITSU LTD 发明人 YAMASHITA ATSUSHI;NAKAMURA TADASHI;MORIWAKE MASARU
分类号 H03M13/23 主分类号 H03M13/23
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