发明名称 SYNTHESIS METHOD OF LOGIC CELL
摘要 PURPOSE:To implement high density, by expressing wiring information in a tree structure with basic gates as constituent elements, comparing searching routs in the structure with the set of the constituent elements, extracting the same constituent element, which can be applied to wiring/wiring, and synthesizing a logic cell. CONSTITUTION:A 4-bit comparator is used as an example. This device is decomposed into basic gates N2N, N3N... based on the information of an equivalent circuit, and a tree structure is formed. Repeating circuits are taken out. Searching routes in the tree structure can be expressed with each set of N2N, N2N, R2N and so on. LISP processing is actually used. The basic gate corresponds to an atom (a basic constituent element of a language). Each set becomes an S type set (a set expressing a logic, which is constituted by the atoms). The processings of the atoms such as OR, AND, exclusive OR are performed. The sets are compared, and the elements having the same constitution are extracted. The repeating sets are combined together. Then, the the series and parallel data among the repeating circuits are arranged, and a logic cell is formed. The basic gates are arranged in correspondence with the features of the extracted logic circuits. In this method the high density of the logic cells can be implemented in the automatic layout.
申请公布号 JPS63129645(A) 申请公布日期 1988.06.02
申请号 JP19860276963 申请日期 1986.11.20
申请人 FUJITSU LTD 发明人 MACHIDA YASUHIDE;SATO SHINJI
分类号 H01L21/82;G06F17/50;H01L21/822;H01L27/04 主分类号 H01L21/82
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