| 摘要 |
PURPOSE:To decrease the circuit scale by providing a parallel/serial conversion section outputting an error location in series, a diagonal element latch section latching diagonal elements of a matrix and a shift number control register controlling the shift number till the inputted data is outputted. CONSTITUTION:A serial data outputted from a parallel/serial conversion section 114 is inputted to the constitution coupling shift number control registers 135-138 in a ring, the diagonal elements of a matrix are latched in the diagonal element latch sections 127-130, the arithmetic operation is advanced along the algorithm of the sweep-out method and data number latched in the shift number control registers 135-138 is decreased sequentially. Thus, a divider 131 and multipliers 132-134 in a Galois field included in the titled missing control circuit are used effectively and the time till the entire error pattern is obtained is suppressed with the constitution where the number of dividers and multipliers in the Galois field is less.
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