| 摘要 |
1296562 Transistors INTERNATIONAL BUSINESS MACHINES CORP 30 July 1970 [6 Aug 1969] 36884/70 Heading H1K The emitter region of a transistor is formed in a pedestal defined by a groove in a major surface surrounding the pedestal so that the emitter junction emerges at the periphery of the pedestal. As shown, Fig. 1 a P-type Si substrate 10 is provided with a thermally grown or pyrolytically deposited mask 12 in which an annular window 14 is photoetched, Step 1. The wafer is then thermally oxidized more rapidly than the masked areas so that an annular recess 18 is formed surrounding a pedestal 19, Step 2. A circular window is formed in the oxide layers and an N+-type sub-collector region 20 is formed by diffusion from the gas phase or from a doped layer or by ion implantation, Step 3. The remainder of masking layer 12 is then removed and an N-type epitaxial layer 24 is grown which reproduces the pedestal, Step 4. An oxide masking layer 26 is formed and a P-type base region 30 is formed by diffusion, Step 5. An N<SP>+</SP>-type collector contact region 44 extending to the sub collector region 20 is formed and an N-type emitter region 34 is formed in the pedestal of the epitaxial layer by diffusion using a masking layer 26a, Step 6. The surface of the wafer is passivated with SiO 2 , Si 3 N 4 or glass layer 36 and emitter, base, and collector contacts 38, 40, 42 are applied, Step 7. The device may be formed as part of an IC with appropriate isolating regions and interconnections which may be multi-level. In alternative Steps 1 and 2 the substrate 10 is covered with a layer 50 of SiO 2 covered with a layer 52 of Si 3 N 4 which is masked with a layer 54 of SiO 2 for etching the annular window so that the oxide layer 56 grows only at the exposed area. In a second embodiment, Fig. 2 (not shown), a sub-collected region is diffused into a substrate and an epitaxial layer grown. SiO 2 covered with Si 3 N 4 is used as a masking layer during oxidation to form the recess, the surface is masked and the portion of the Si 3 N 4 layer covering the pedestal is removed. Ga is then diffused through the bulk of the oxide layers to form the base region, the remaining Si 3 N 4 layer acting as the mask, the oxide layer covering the top of the pedestal is removed. As and/or P is diffused-in to form the emitter region, the remaining oxide layers acting as the mask, and the device is passivated and contacted. In a further embodiment, Fig. 3 (not shown), a sub-collector zone is diffused into a substrate, an epitaxial layer is grown and base and emitter regions are formed by planar diffusion. The wafer is then masked and an annular window is opened which surrounds the emitter region, 0 or N ions are implanted to a depth greater than that of the emitter region, and the wafer is heated to react the implanted ions with the Si to form an annular SiO 2 or Si 3 N 4 ring filling a recess surrounding a pedestal containing the emitter. |
