| 摘要 |
PURPOSE:To reduce the parasitic resistance, especially the source resistance, to shorten the length of a gate and to reduce a short-channel effect by providing an n-type layer formed from the surface of a semi-insulating GaAs semiconductor substrate down to a prescribed depth, and an n<+> source region and a drain region formed in contact with a gate electrode buried into a recess formed from the surface of the n-type layer to a position before its bottom, and in contact with an insulating layer surrounding the circumferential side of the gate electrode. CONSTITUTION:A mask 22, for injection use, of SiO2 is formed on an semi- insulating GaAs substrate 10, and ions of Si are implanted. As a replacement for the mask 22 for implantation use, a mask 24 for etching use is formed; a recess 26 for formation of a gate part is formed ; ions for a channel (n-layer) use are implanted; the assembly is annealed. SiO2 is deposited; the deposited layer is etched over the whole thickness. A layer 28 where tungsten silicide is deposited is coated with a photoresist layer; a resist layer 30 and the WSix layer 28 are etched back over their thickness on n<+> layers 12a, 12b. An SiO2 layer 32 is formed on the surface; windows for a source and a drain are opened; AuGe/Au is deposited; a source electrode and a drain electrode S, D are formed.
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