| 摘要 |
A method for dynamic edge synchronisation of two quasi-synchronous signals is described, the edges of which can temporarily exhibit certain time offset. This is intended for supplying a comparator circuit, followed by a failsafe memory, with synchronous signals. The failsafe memory should only be allowed to drop out when the non-equivalence of two signals exceeds a certain time. According to the invention, the signals are conducted via a two-channel synchronisation stage 1 in which the signal arriving first is in each case switched through directly on its channel and triggers with its edge associated timing elements (MF1 to MF4) which output a defined bridging pulse (TY) on the other channel for switching-on synchronisation, within which the subsequent signal must also have begun on this channel, and that the signal in each case going to zero first of the one channel triggers turn-off timing elements (MF5, MF6), which output a defined bridging pulse (TZ) to this channel for turn-off synchronisation, within which the signal on the other channel must also have gone to zero. The subclaims contain arrangements for carrying out the method. The outlay is advantageously small and, in addition, can be implemented with simpler, non-failsafe technology. <IMAGE>
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