| 摘要 |
PURPOSE:To perform data transfer required for area swapping, etc., at high speed, by providing plural memory address generators provided with two data buses and which designate an area in a source or a destination plane to one of the two address buses. CONSTITUTION:Plural bit map memory planes 30-i are connected to a memory bus 50. The mutliplexer(MUX)32 of the plane 30-i selects address buses 52a and 52b, and the MUX33 selects control buses 53a and 53b. In a computing element ALU35, the data 51a or 51b and a memory block 31 are connected to the input side of the element, and whose output side is connected to a bus 51b or 51a. A control processor sets the address generators 62 and 63 so as to generate addresses setting a memory area that is a source area as an object, and the address generator 64 so as to generate the address setting the memory area that is a destination area as the object. Thus, it is possible to transfer data required for the area swapping, etc., at high speed.
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