| 摘要 |
A circuit for simultaneously obtaining in parallel signals constituting a time division multiplexed signal comprises a first delay circuit supplied with an input time division multiplexed signal and having a delay time corresponding to a duration of one of the signals constituting the time division multiplexed signal, a switching circuit supplied with an output signal of the first delay circuit and the input time division multiplexed signal for carrying out a switching operation for every constant repetition period so as to simultaneously output signals in parallel, a second delay circuit supplied with the output signal of the first delay circuit and having a delay time identical to that of the first delay circuit, an operation circuit supplied with the input time division multiplexed signal and an output signal of the second delay circuit for carrying out a subtraction or an addition, and a non-linear characteristic circuit having an input versus output characteristic which varies non-linearly. The non-linear characteristic circuit is supplied with an output signal of the operation circuit and feeds back an output signal thereof to the time division multiplexed signal.
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