| 摘要 |
PURPOSE:To improve system response by selecting data in the unit of bits while each bit of an address bus and a data bus is made correspondent to each other in the descending order of the bit number so as to enable both data to be transferred in the lump. CONSTITUTION:In accessing an input/output controller from a CPU via a bus extender 10 and an interface 14 and the CPU uses a 32-bit address and a 32-bit data, for example, a multiplexer 13 selects alternately the data of 32-bit of an address bus and the data of 32-bit of a data bus in time division to transfer them through a signal line in 32-bit of an interface 14. Then the multiplexer 13 is controlled to select address buses A0-A15 as to signal lines AD0-AD15 of the interface 14 and data buses D15-D0 as to signal lines AD16-AD31. Thus, the data is transferred simultaneously through the address and data buses.
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