| 摘要 |
An echo cancelling system incorporated in a conventional echo canceller with additional circuitry to provide tracking and compensation for drifting of any D.C. offset generated. Upon initial energization of the system (i.e. before data signals are processed thereby) an output signal e1k from an error signal input device represents a D.C. offset value generated by the components of the system. This value is stored in a D.C. offset register, the loading of which is controlled by a load/inhibit signal. Refining of the stored value during data processing is achieved using predetermined increments DELTA 1 for half-duplex mode and DELTA 2 (of smaller size) for full-duplex mode.
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