Method and apparatus for a constant frequency clock source in phase with a variable frequency system clock

摘要

A clock apparatus provides variable frequency system clock signals for synchronizing the operation of data processing apparatus and constant frequency timing signals, in phase with the system clock signals, for controlling the operation of an interval timer or related apparatus. The variable frequency system clock signals are produced by placing a controllable divider network in the phase locked loop. The input signals to the controllable divider network are distributed as the system clock signals. The constant frequency is obtained by distributing count signals from the controllable divider network of the phase locked loop circuit to a plurality of comparator circuits and output signals from the comparator provide a multiplicity of timing intervals that result in the constant frequency signals. The timing intervals are determined by the control signals that are applied to controllable divider network and to a plurality of divider circuits associated with the comparator circuits. The control signal is divided by the divider circuit and the resulting value entered in the comparator circuit where the value is compared with the count from the controllable divider network. A distribution network, used to provide a delay in the distribution of the system clock signals, thereby synchronizing components of the data processing system, is placed in the phase locked loop to insure that the signal to the constant frequency signals and the system clock signals are in phase.