发明名称 |
Parallel multiplier array with foreshortened sign extension |
摘要 |
A compact rectangular parallel multiplier array of Booth summation cells includes along a left edge a cell which reduces to two the number of sign-extension bits sufficient to generate subsequent intermediate products. The cell employs optimized logic circuitry which generates a sum, a carry and a guard bit for use during generation of the next most-significant intermediate product.
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申请公布号 |
US4748582(A) |
申请公布日期 |
1988.05.31 |
申请号 |
US19850747073 |
申请日期 |
1985.06.19 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
NEW, BERNARD J.;FLAHERTY, TIMOTHY J. |
分类号 |
G06F7/53;G06F7/508;G06F7/52;G06F7/533;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/53 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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