| 摘要 |
The basic cells of a parallel multiplier are arranged into arrays corresponding in number to the number of bits of multiplier data Y and multiplicand data X. Multiplicand data supply lines supply bit data Xi corresponding to the basic cell of the multiplicand data X, its inverted data &upbar& X, bit data Xi-1 one digit lower than said corresponding bit, and its inverted data Xi-1 to each of the basic cells. Decoders decode multiplier data Y based on the Booth's algorithm. These decoders supply a prescribed select signal to the basic cells. The basic cells comprise a selecting circuit for selectively inputting one of data Xi, &upbar& X, Xi-1, Xi-1 and "0" according to the select signal from the decoders, and a full adder. The full adder receives the data input by the selecting circuit as the augend data and receives the addend and carry data from the previous row of basic cells. The full adder adds the augend, addend and carry data, and outputs sum and carry data.
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