| 摘要 |
PURPOSE:To prevent a steady-state current from flowing even if a tri-stage buffer is in a high level or low level state by setting a bus line to the light or low level when the tri-state buffer connected to the bus line is in high impedance state. CONSTITUTION:A memory cell 3, n-set of tri-state buffers 1-1-1-n and a 2nd gate 2 are connected to a bus line 10. A level '1' is written in the memory cell 3 constituted in this way by bringing the terminal to the high level forcibly and '0' is written in bringing it to the low level. In setting the conductivity of transistors (TRs) 311, 312 and 321, 322 sufficiently smaller than the conductivity of each TR of the tri-state buffers 1-1-1-n, '1' is written in the memory cell 3 when the output of the tri-state buffer is at the high level and '0' is written in at the low level. Even when the tri-state buffer is changed to the high impedance state, since the memory cell 3 keeps the preceding '1' or '0', the state of high impedance is prevented.
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