| 摘要 |
PURPOSE:To elevate testing efficiency by constituting an inspection device with a defect analyzing memory to store the information of all measured memory element that they are whether non-defective or defective, and with a fail bit counter to store how many defects exist in each memory address line, and with a fail address memory device to store this. CONSTITUTION:The non-defective or defective state of all the address lines of the measured memory are written in the defect analyzing memory 122 as they are, through a selector 121, and at the same time, the address generated in the internal part of an address generator 144 is selected by the selector 121, and the data of the line, in which the fail bit exists, is inputted to a counter memory 131, a fail data memory 141 and the counter memory 142, and the memory 131 adds the fail bit by using an adder 132 at every occurrence of the fail bit, and inputs the counted result to the memories 141 and 142. Afterwards, a memory map is produced, and if the number of the fail bits more than a prescribed value exists, this address is designated and exchanged with a spare memory.
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