发明名称 ENCODER
摘要 PURPOSE:To prevent the occurrence of level inversion at decoding by sending a data of bit number (m) while it is converted into a data whose absolute value is lower by one step and has other bit number (m). CONSTITUTION:An input signal A is subtracted (16) from a predicted value B, its output C is an 8-bit signal being the synthesis of the signal A and the decoding B by one sample, the signal is compressed into 4-bit by ROMs 19, 20 and fed to a selector 22. The ROM 20 converts the signal into a 4-bit signal whose absolute value is smaller by one step by means of a prescribed conversion characteristic. A ROM 23 expands a signal from the ROM 19 into an 8-bit signal, the predicted value B is added (24) thereto and an MSB of the addition output is compared (26) with the MSB of the signal A, and the absolute value of the signal A and the reference value 25 are subject to level comparison 27, each comparison output is given to a selector via an AND gate 28. When the absolute value of the signal A is larger than the reference value 25, the output of the ROM 20 is selected and sent and when the output of the ROM 20 is smaller, the output of the ROM 19 is sent.
申请公布号 JPS63126323(A) 申请公布日期 1988.05.30
申请号 JP19860271811 申请日期 1986.11.17
申请人 HITACHI LTD 发明人 OKAMURA FUJIO;NISHIMURA KEIZO;FURUHATA TAKASHI
分类号 H03M3/04 主分类号 H03M3/04
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