发明名称 OPERATING STATE MONITORING CIRCUIT FOR IGBT
摘要 PURPOSE:To detect latch-up phenomenon without fail, by monitoring the state by the use of the voltage across and the current between the gate and the emitter of an insulated gate bipolar transistor. CONSTITUTION:In a power converter, etc., such as an inverter for driving an AC motor, the abnormal state of an insulated gate bipolar transistor (hereinafter referred to as IGBT) 1 is detected. For this purpose, a state monitoring circuit 2 connected to a gate drive circuit 3 of an IGBT 1, a current detector 4 and an exclusive OR (EOR) gate 5 are provided. The abovementioned detector 4 outputs logical '1' when the collector current of the IGBT 1 is 0, while the monitoring circuit 2 outputs logical '1' when the gate is 0. Thus, since no collector (emitter) current will be reduced even if the latched-up IGBT 1 sets up the gate voltage for 0. it can be easily detected by logical operation.
申请公布号 JPS63124765(A) 申请公布日期 1988.05.28
申请号 JP19860268671 申请日期 1986.11.13
申请人 FUJI ELECTRIC CO LTD 发明人 KOSAKA KENJI
分类号 H02M7/537;H02M1/00 主分类号 H02M7/537
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