| 摘要 |
PURPOSE:To converge the phase difference to zero quickly by deciding whether or not a phase difference between an output clock of a voltage controlled oscillator (VCO) and a reference clock is within a region zero and continuing to vary a VCO control voltage so as to reduce the phase difference at the outside of the range thereby varying the frequency of the VCO. CONSTITUTION:In case of the decision of the delay state in a phase polarity decision circuit 3, a control voltage generating circuit 6 changes a voltage to increase the frequency of the VCO 1 and in case of the decision of leading state, the voltage is changed to decrease the frequency conversely. In case of the decision of phase difference zero by a phase difference detection circuit 2, the operation of the control voltage generating circuit 6 is stopped to hold the control voltage just before the operation stop. Thus, the phase difference is converged to zero region by continuing the operation above. Moreover, the polarity change in the phase is decided in the circuit 4 and the control voltage approaches a prescribed value at every change in the control voltage generating circuit 6.
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