| 摘要 |
PURPOSE:To improve the manufacturing yield, to facilitate the design and to reduce the occupied area shared in an integrated circuit by selecting the capacitance of a capacitor Ct to a value substituted to a specific calculation formula, forming a possibly high oscillation frequency, providing a frequency division counter to the next-stage of the oscillation section thereby obtaining a clock having a desired period. CONSTITUTION:1st and 2nd inverters 1, 2 connected in series, a capacitor Ct and a resistor Rt constitute the oscillation section. The capacitor Ct is selected near a limit where the oscillation frequency is deviated from a calculation formula I. Moreover, an oscillation output having a desired period is extracted from an output terminal of a frequency division counter 3 connected to an output terminal of the 2nd inverter 2. Through the constitution as above, the period T of the desired low, frequency oscillation output is obtained from the formula I. The frequency division counter 3 consists of conventional flip-flops TFFs and (n) is selected freely by the bit number. Thus, the oscillation circuit offering ease of design is obtained and the occupied area in the integrated circuit is minimized.
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