发明名称 VARIABLE DELAY CIRCUIT
摘要 PURPOSE:To accurately retard a high speed signal variable by providing at least >=2 ground means reflecting an inputted signal onto a transmission line having a uniform characteristic impedance and extracting a reflected wave retarded in response to the position of the ground means provided onto the transmission line. CONSTITUTION:With a switch 4a closed, a negative pulse 101a of a driver 1 propagates onto a transmission line, the polarity is inverted at the position of the switch 4a and is reflected toward the driver 1. The reflected positive pulse 101b is compared with a comparison voltage 102 by a comparator 2 and a negative pulse 103b is outputted. With a switch 4b closed, the similar operation to that above is applied, and the reflected positive pulse 101c is inputted to the comparator 2 while being retarded by a time of a reciprocation of the signal between the switches 4a and 4b more than the case with the switch 4a closed. Since the length of transmission line through which a signal propagates between the driver 1 and the comparator 2 is varied depending on the position of the switch 4 connecting the transmission line 3 to ground, the input signal is delayed variably with high accuracy.
申请公布号 JPS63124604(A) 申请公布日期 1988.05.28
申请号 JP19860269619 申请日期 1986.11.14
申请人 HITACHI LTD 发明人 HAYASHI YOSHIHIKO
分类号 H01P9/00;H03H7/30 主分类号 H01P9/00
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