| 摘要 |
PURPOSE:To take the synchronization between an input clock and an output clock in a short locking time by sectioning the phase difference between the input clock and the output clock so as to vary the frequency division ratio of the frequency divider in proportion to the phase difference. CONSTITUTION:In the phase of a clock 9 is led with respect to the phase of a clock 6, a decoder control circuit 3 outputs a decode enable signal 10 just after a time when a shift register 2 is shifted by 2-bit just before the leading of the clock 9. A decoder 4 receiving a decode enable signal 10 reads the content OH of the shift register 2. When the phase of the clock 9 is almost in matching with the phase of the clock 6, the decoder 4 reads the content 3H of the shift register 2. When the phase of the clock 9 is retarded to the phase of the clock 6, the decoder 4 receiving the decode enable signal 10 reads the content FH of the shift register 2.
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