| 摘要 |
PURPOSE:To obtain an error detection and correction circuit which is compara tively small in size by providing the error detection and correction circuit corre sponding to divided data in respective sectors, and detecting and correcting errors from an added parity signal at every data. CONSTITUTION:For writing data of 512 bytes in a data field, data DATA 1 of 256 types, the parity signal ECC 1 consisting of 4 bytes, data DATA 2 of 256 bytes and a parity signal ECC 2 consisting of 4 bytes are sequentially arranged in the format of a write signal WD. If the counted value of a byte counter BTC shows 259 including the parity signal ECC 1 for reading, a block counter BTC changes logic '0' to logic '1' and clears a byte counter BTC and an ECC circuit. With fetching continuously supplied read data DATA 2 and the parity signal ECC 2, and with using them for decoding, errors are detected and corrected.
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