| 摘要 |
PURPOSE:To complete the synchronization between plural data and clocks at the same time by selecting the synchronization between plural retarded clocks and data duplicatedly. CONSTITUTION:An input data D1 and a clock C1 oscillated by a voltage controlled oscillator 4 are synchronized. Delay elements 81-8n retard the clock C1 by n-stage to output clocks phi1-phin. A synchronizing detector 6 detects the synchronization between the data D1 and the clock C1 and synchronizing detectors 60-6n detect the synchronization between the input data D2 and the clocks phi0-phin respectively, where the phi0 is a clock without delay. A discrimination circuit 9 discriminates the synchronization between the data D1 and the clock C1 and between the data D2 and the clock phi0 and phin by an output SX of the detector 6 and the outputs S0-Sn of the detectors 60-6n, outputs a synchronization end signal SZ at the output terminal 10, outputs signals A0-An selecting one of the clocks phi0-phin to the selection circuit 11 and outputs any of the clocks phi0-phin as the clock C2. Thus, the synchronization of plural signals is finished simultaneously. |
