发明名称 BUS CONTROL ERROR DETECTION CIRCUIT
摘要 PURPOSE:To prevent malfunction and to facilitate pinpointing troubled parts by providing a simultaneous accept detection circuit which detects whether accept signals that are transmitted to an information processor is simultaneously transmitted to >=two devices. CONSTITUTION:The simultaneous accept detection circuit 40 is provided, and it receives the accept signals 201-204 and checks whether they are transmitted to >=two devices simultaneously. AND circuits 41-46 receive the accept signals 201-204, take their AND and transmit check signals 141-146. An OR circuit 47 receives the check signals 141-146, takes their OR and simultaneously transmits an accept error signal 147. When the accept signals to allow the use of a bus are simultaneously transmitted to >=two information processors, the fact is detected. Thus malfunction is prevented, and troubled parts can be pinpointed in the entire system.
申请公布号 JPS63121953(A) 申请公布日期 1988.05.26
申请号 JP19860267940 申请日期 1986.11.11
申请人 NEC CORP 发明人 YAMAUCHI MAKOTO
分类号 G06F13/00;G06F13/20;G06F13/36 主分类号 G06F13/00
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