| 摘要 |
PURPOSE:To eliminate one cause contributing to the overhead of system by providing a 2nd readable associative memory CAM with a physical address storage part and 1st CAM with both a valid bit reset circuit and a logical address storage part. CONSTITUTION:When a rewritable signal is set to Hi to rewrite address information, a rewrite control part 13 selects an appropriate word, generates a rewrite control signal 16 and writes a new logical address and a physical address for the word through a logical address input part 23 and a physical address input part 24. If page-out occurs to invalidate only address information whose validity is lost, a page signal 19 is set to Hi, and the physical address input part 24 inputs an out-of-page physical address and retrieves by the address. A physical address coincidence detection signal 15 invalidates only a corresponding valid bit.
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