| 摘要 |
PURPOSE:To decrease the capacity of flag memory by providing a flag write address generator and an address conversion circuit. CONSTITUTION:With an inner block address inputted to a terminal 2, an address by a data number in an inner block is generated sequentially from a data write address generator 3 and a data 6 is written sequentially in a data memory 8. Further, one address per one inner block is outputted from a flag write address generator 4 and a flag 7 is written in a flag memory 9. The written data is read sequentially from an address of the read data address 14 generated sequentially by a data read address generator 13 based on a video synchronizing information signal 17. The flag is converted into a flag read address 16 by a flag read address conversion circuit 15 based on the address 14 and the flag corresponding to the data is read. Thus, the capacity of flag memory is reduced remarkably.
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