| 摘要 |
PURPOSE:To speedily obtain edge coordinates and the coordinates of an picture element at a specific logical level by providing an address counter, a multiplexer, an instruction storage FIFO memory, an instruction latch, a control latch, a PROM, a result coordinate storage FIFO memory and a control circuit. CONSTITUTION:A CPU 10 writes first (x2-x1)-edge search instructions and second stop instructions into the instruction storage FIFO memory, and presets coordinates x1 and y1 to counters (x) and (y) in the address counter 2. The CPU 10 transmits analysis start instructions to a picture element analysis circuit through a control circuit 9, and renders the circuit 9 to analyze the edge coordinates. While the analysis results are written in the result coordinate storage FIFO memory 8 after receiving an end signal from the picture element analysis circuit, results are read out and stored in the memory. Such procedures are repeated and picture elements are analyzed until the reading of an address (y) counter reaches y2. In such a way hardware executes processing to obtain the edge coordinates and the coordinates of the picture element at the specific logical level, all of which are required for analyzing picture element. Hence the processing are speed up.
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