发明名称 MEMORY ACCESS SYSTEM
摘要 <p>PURPOSE:To reduce memory competition and to improve system performance by grouping plural processors, associating plural memories with the groups one by one, giving the same memory capacity to each group and allocating the same address to the groups. CONSTITUTION:When a processor 1 reads data out of the memory, a memory access control part 7 turns on a signal line 15, and gives a read command R to the memory 5 and simultaneously gives a read address A to the memory 5 through a signal line 11. When the processor 1 writes data in the memory, the memory access control part 7 turns on a signal line 16, and gives a write command R to the memories 5 and 6 and simultaneously gives write address A and write data D1 to the memories 5 and 6 through a signal line 14. A processor 2 accesses the memory in the same manner as the processor 1, and processors 3 and 4 do the same action except for reading data in the memory 6.</p>
申请公布号 JPS63123152(A) 申请公布日期 1988.05.26
申请号 JP19860267774 申请日期 1986.11.12
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 HIRANO MASANORI
分类号 G06F15/16;G06F12/00;G06F12/06;G06F13/16;G06F15/167;G06F15/177 主分类号 G06F15/16
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