发明名称 SAMPLE/HOLD CIRCUIT
摘要 PURPOSE:To reduce an abnormal signal in an output signal by connecting a resistance in parallel to a sample/hold capacity and increasing the drain current of a transistor. CONSTITUTION:By connecting the resistance 2 in parallel to the sample/hold capacity 1, a 'flaw' can be reduced. In this case, a drain current-drain voltage characteristic is only changed linearly to the change of a Vg (gate voltage), therefore, the input/output characteristic of the transistor 3 is not changed. Thereby, in a sample/hold circuit, an output noise level can be reduced without sacrificing the input/output characteristic and the abnormal signal in the output signal can be reduced.
申请公布号 JPS63121199(A) 申请公布日期 1988.05.25
申请号 JP19860265887 申请日期 1986.11.08
申请人 SONY CORP 发明人 SHOJI KAZUMI;KUNIMOTO SATOSHI
分类号 G11C27/02 主分类号 G11C27/02
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