| 摘要 |
PURPOSE:To reduce the charging/discharging current of the parasitic capacitance of an output signal line and to improve the response speed and to reduce the current consumption by limiting the potential in the high level of an output node to a prescribed value. CONSTITUTION:If a data signal D rises to the high level when an output enable signal OE is in the high level, a P-channel transistor TR TP is turned on because the outout of a NAND gate 2 goes to the low level, and an output node NO starts rising to the high level. When the level of the output node NO exceeds the logical threshold of an inverter 4 on the way of this rise, the output of the inverter 4 goes to the low level and the output of a NAND gate 2 goes to the high level, therefore, the P-channel TR TP is turned off. Thus, the response speed is improved and the current consumption is reduced because the output node NO is stabilized in the logical threshold level of the inverter 4 and the charging/discharging current of the parasitic capacitance of the output signal line is reduced. |
